Model 4012 VFTLP+ ™ Device Testing

Overview of the VFTLP+ ™ test

The VFTLP+ ™ Test System is unique in that it provides a few very fast test pulse risetimes which simulate the CDM threat.  Our VFTLP+ ™ system also incorporates even faster current and voltage sensors to accurately identify the silicon response to this very fast test pulse. For minimal measurement errors we have found that connections to wafers, chips, or naked dies must be made with microwave probes. The needles on these probes provide low resistance connections to bond pads with minimal reactive parasitics but are only available with fixed needle spacings.

The typical microwave probes we use have spacings of 50, 100, 125, 150, 175, 225, 250, 350, and 1250 micron.

Because VFTLP+ ™ testing needle spacing is fixed, connections to your pads must be made with the above selection of needle spacings. Please supply information on your pad spacing to help us prepare testing of your silicon. Please also identify which pads you want tested and at the polarity (+ & -) orientation desired for each pair of pads.

Requirements for the VFTLP+ ™ test

  • Wafer – pad sizing, spacing, and map layout indicating (+ & -) pads
  • Wafer segment – pad sizing, spacing, map layout and a description of the dies you want tested indicating the (+ & -) pads
  • Naked Die Test – pad sizing, spacing, map layout and a description of the dies you want tested indicating the (+ & -) pads

Contact us to find out more!

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