TLP+ ™ Testing

Model 4002/4003 TLP+ ™ Device Testing

Overview of the TLP+ ™ test

The basic purpose of the TLP Test System is to provide measured I / V characteristics resulting from pulse current threats while monitoring leakage values. This allows the designer to determine whether the implementation of his ESD protection elements gives the electrical characteristics desired. The results of TLP testing can be equated to failure levels found with HBM testing.

HBM testing is an approximate measure of how much ESD threat your protection can withstand. TLP can precisely measure the level of failure and help you understand why it fails when it does. With precisely controlled risetime pulse threats, it also will let you see the complete I/V curve to understand exactly your design responds when stressed with different risetime pulses.

Requirements for the TLP+ ™ test

  • DIP Packaged device – Pin-out and numbers of pins to be tested indicating (+) and (-) pins
  • BGA Package – BGA map and description of balls to be tested indicating (+) and (-) pins
  • Wafer – Pad size, spacing, and map layout indicating (+) and (-) pins
  • Wafer segment – Pad size, spacing, map layout, & description of dies you want tested indicating (+) and (-) pins

Contact us to find out more!

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