Model 4012 VFTLP+™

The Model 4012 VFTLP+™ test system was developed in early 2000 to add high speed measurements to the usual I-V plot, to measure and record the real TDDB waveform which causes oxide failure.

  • Accurate measurements of this waveform have finally been identified by Barth Electronics Inc. and CDM protection can now be based on known dimensional design parameters. We identify the response of your CDM protection circuits with 100ps risetime pulses which simulate the real CDM test. This is the only way with which to provide the total gate oxide threat voltage data.
  • Convenient, precise, repeatable operation
  • Computer controlled for automated testing
  • VFTLP+™ Accessories
  • VFTLP+™ Software

Why the Plus(+) in VFTLP+™?

 

Visit us at the EOS/ESD Symposium!

We will be attending the 2017 EOS/ESD Symposium in Tucson, AZ, September 11-13. Stop by booth 703 at the Westin La Paloma in Tucson. Monday 6pm-9pm; Tuesday 9:30am-5:30pm; and Wednesday 8:30am-1:30. Hope to see you there!

Model 4012 VFTLP+ Specifications

Model 4012 VFTLP+™ specifications in printable PDF format.
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Companies using the Model 4012 VFTLP+

Current list of companies using the Mode 4012 VFTLP+™ test system.
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Model 4012 VFTLP+ Device Testing

Information on Model 4012 VFTLP+™ device testing.
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